When integrating embedded SSD technology into industrial applications, several factors can contribute to the relative performance and endurance of the device. Things like random vs. sequential transfers and file/transfer size can have dramatic impacts on realized performance and overall endurance. Large file transfers comprised of larger sector data and transferred sequentially are ideal. Graphics, audio and video are ideal examples of larger sector sequential data. Conversely, small file transfers comprised of smaller sector data and transferred randomly has the most deleterious impact on performance and endurance.
Most data logging is comprised of small sector random data transfers. Firmware variations optimized for small (even single) sector random data applications can help improve performance and maintain endurance. Still, other best practices should be implemented in parallel when architecting host systems.
Wherever possible, operate in DMA Mode (UDMA if possible, MWDMA if not). MWDMA Mode 4 operates with an 80ns cycle time and UDMA Mode 4 operates with a 60ns per 2 cycles. In addition to faster throughput, operating in DMA mode reduces the time the host processor must spend waiting to receive or transfer data, which can help increase overall system performance.
Page Boundary Alignment
Where possible, it is best to align data transfers with 2KB, 4KB or 8KB boundaries depending on which flash media type is being used (2KB is usually used below 1GB and 4/8KB on higher capacities). If data transfers are not aligned within 2/4/8KB boundaries, read-modify-write operations become necessary, which increases latency and slows overall performance.
Root Directory/FAT Updates
Where possible, minimize or consolidate accesses to these structures that are used on the flash media by the operating system. Typically, these accesses are small (often just one sector) in size, and they carry a performance penalty similar to that of small random write accesses outlined previously.
Operating in the default 16-bit mode provides about twice the performance of 8-bit mode.
Status Register Polling
Drivers should be written so that the card/drive’s status register is polled before issuing commands or initiating data transfers, rather than using hard-coded wait loops. Polling for 0x50 in the status register before issuing a command and then polling, again, for 0x50 before initiating a data transfer will ensure both reliable operation and optimal performance.