Comparing DDR1/2/3 DRAM Technologies

This page provides information about the differences in DRAM technologies and shows you new support features for new DRAM technology.

DRAM Technology Comparison	SDR DRAM	DDR SDRAM	DDR2 SDRAM	DDR3 SDRAM
Module Bandwidth (MB/s) Module speed bin, 64bit data bus	528 800 1064	PC-1600 PC-2100 PC-2700 PC-3200	PC2-3200 PC2-4200 PC2-5300 PC2-6400	PC3-6400 PC3-8500 PC3-10600 PC3-12800
Data rate (Mb/s per pin), Chip speed bin (*Note 3)	PC66 PC100 PC133	DDR-200 DDR-266 DDR-333 DDR-400	DDR2-400 DDR2-533 DDR2-667 DDR2-800	DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Clock (Mhz)	66 100 133	100 133 166 200	200 266 333 400	400 533 666 800
Module ranks (# of chip select lines)	1, 2	1, 2, 4	1, 2, 4	1, 2, 4
Module data bus width (I/O organization)	x64, (x72 with ECC)	x16, x32, x64, (x72 with ECC)	x16, x32, x64, (x72 with ECC)	x16, x32, x64, (x72 with ECC)
JEDEC Modules and JEDEC Form Factors			VLP	VLP
	RDIMM	RDIMM	RDIMM	RDIMM
	UDIMM	UDIMM	UDIMM	UDIMM
	SODIMM	SODIMM	SODIMM	SODIMM
			SO-CDIMM	SO-CDIMM
			SO-RDIMM	SO-RDIMM
		microDIMM	microDIMM	microDIMM
			mini-DIMM	mini-DIMM
			FB-DIMM
		16b-SODIMM	16b-SODIMM	16b-SODIMM
			32b-SODIMM	32b-SODIMM
		32b-DIMM
Module Thermal Sensor			SODIMM FB-DIMM	SODIMM FB-DIMM
Module pin-out (*Note 1)			New	Same as DDR2
Module Densities	up to 256MB	128MB to 2GB	256MB to 4GB	256MB to 8GB
Chip Densities	32Mb to 256Mb	128Mb to 1Gb	256Mb to 2Gb	512Mb to 8Gb
Chip Density @ Lowest Cost per Bit	128Mb	256Mb	512Mb	1Gb
Chip data bus width (I/O organization)	x4, x8, x16	x4, x8, x16	x4, x8, x16	x4, x8, x16
Voltage (VDD = VDDQ/[V])	3.3 (+/- 0.3)	2.5 (+/- 0.2)	1.8 (+/- 0.1)	1.5 (+/- 0.075)
% Power Reduction from previous generation (VDD only) (*Note 2)		32% reduction	39% reduction	20% reduction
On-die Thermal Sensor (ODTS)				Each DRAM
Interface	LVTTL	SSTL_2	SSTL_18	SSTL_15
DRAM Banks (inside the chip)	2/4	4	4 (8 for 1Gb)	8
Prefetch (bits)	1	2	4	8
Burst length (*Note 5)	1, 2, 4, 8 (page)	2, 4, 8	4, 8	8 (4 burst chop)
Bidirectional strobe	None	Single Ended (SE)	SE, Differential optional	Differential only
DQ driver strength/calibration	Wide envelope	Narrow envelope	18 Ω ,OCD calibration	34 Ω , ZQ-pin self-calibration
Termination		only on MoBo	MoBo/ODT values = 50, 75, 150, or “off””	DIMM/Dynamic ODT
Read Latency (*Note 3)	CL = (1), 2, 3	CL = (1.5), 2, 2.5, (3)	CL = (2), 3, 4, 5	CL = 5, 6, 7, 8, 9, 10, (11)
Read Additional Latency	-	-	AL = 0, 1, 2, 3, 4	AL = 0, CL-1, CL-2
Write Latency	0	1	RL-1	5, 6, 7, 8 + AL
Data mask	Yes	Yes	Yes	Yes
Interrupts	Yes	Yes	Wr-Wr, Rd-Rd 4n only	Burst Chop for Rd and Wr
DRAM Package (monolithic)	TSOP-54	TSOP-66, BGA	FBGA only	FBGA only
DRAM ballout (On-DIMM Mirror friendly)	No	No	No	Yes
Asynchronous Master RESET pin	No	No	No	Yes. Interrupt reset for system flexibility.
Support of system level flight time compensation	No	No	No	Yes
DRAM CWL (programable CAS Write Latency) per speed bin (*Note 6)	No	No	No	Yes
On-die IO calibration engine	No	No	No	Yes. (data auto-calibration on the output buffer for high speed interface operation through ZC)
Fly-by CAC (command/address/control) bus with On-DIMM termination	No	No	No	Yes
Read/Write Leveling	No	No	No	Yes
Memory sockets per channel (*Note 4)	4	4	4	4/2
High precision calibration resistors on the DIMM	No	No	No	Yes

Notes:

1. DDR2 and DDR3 UDIMMs and RDIMMs have a 240-pin, 1.0mm pitch memory sockets.

2. DDR3 may be as much as 30% reduction over DDR2 at the same speed, when considering lower IDD currents and other DDR3 architectural changes. DDR3-1600 is at the same power level, as DDR2-800.

3. DDR3 has higher CAS Latency then DDR2: DDR3-800 (5-5-5), DDR3-1066 (7-7-7), DDR3-1333 (8-8-8),
DDR3-1333 (9-9-9).

4. The memory sockets (slots) per channel is memory controller and motherboard dependent. RDIMMs may have more slots then UDIMM. Faster and higher density DIMMs may require less slots per channel.

5. “DDR3 Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]“.

6. DDR3 Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600).